As RISC-V moves from experimental silicon to mass-market industrial applications, the availability of proven, safety-certified Real-Time Operating Systems (RTOS) is a key enabler for adoption. Eclipse ThreadX (formerly Azure RTOS) has long been a cornerstone of the embedded industry. Yet, its immature support for the RISC-V ISA, particularly 64-bit implementations, remained a barrier for high-performance adoption.

In this session, you will learn how 10xEngineers, in collaboration with the Eclipse ThreadX project team, brought first-class RISC-V support to the ThreadX kernel. You will go on a deep dive into the architectural challenges of porting the kernel's core components to both RV32 and RV64, including context switching, interrupt nesting, and timer management tailored for the RISC-V privileged architecture. You will also explore the practical enablement of this port on the SpacemiT K1 SoC (Banana Pi BPI-F3), bridging the gap between virtual prototyping in QEMU and physical hardware deployment. Finally, you will gain insights into the low-level kernel modifications required for RISC-V compliance and discover a roadmap for deploying ThreadX in the next generation of RISC-V embedded systems.