Modern processors delegate power and thermal management to dedicated Power Control Systems (PCS), communicating through kernel-mediated interfaces such as SCMI or the emerging RPMI.
Prior work has shown that end-to-end control quality is dominated by the power-management policy rather than by interface latency, leaving room to choose communication paradigms based on flexibility rather than raw latency.
We integrate Micro XRCE-DDS on ControlPULP, a RISC-V–based PCS, connecting it to a user-space Agent on an ARM host via a custom shared-memory transport.
This design removes protocol logic from kernel drivers and naturally supports multi-controller coordination through a shared middleware layer. Experiments on a ZCU102 FPGA at 20 MHz show 490 μs of active processing per publication, 0.8 MB/s throughput, and a memory footprint under 11.2 KB for 32 topics. The resulting latency is comparable to SCMI [1] while enabling a more flexible communication model.