feixiaolong
I possess 14 years of expertise in high-performance CPU design, specializing in high-performance core development and inter-core interconnect buses. Throughout my career, I have led the development of multiple processor cores across different instruction sets, taking them from design to successful tape-out and final deployment in sectors including finance, consumer electronics, industrial control, and the Internet of Things (IoT). I have also participated in several national "Core and High-Base" initiatives and hold over 15 granted invention patents
Session
As the RISC-V software ecosystem achieves maturity for high-performance computing, the demand for production-ready, competitive processor cores has reached a critical point. This presentation introduces the X200, our flagship RISC-V core, which has completed its entire development cycle and is now ready for deployment. We provide a comprehensive overview of the X200's journey, from its ambitious design goals to final GDS layout. The session details its advanced multi-stage pipeline, sophisticated memory subsystem, and scalable multi-core interconnect fabric. We present a transparent competitive analysis, share key benchmark results, and reveal detailed Power, Performance, and Area (PPA) data verified from the final layout. Attendees will gain a clear understanding of the X200's capabilities and its readiness to power next-generation SoCs.