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UID:pretalx-eu-summit-2026-MQJFNF@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T131000
DTEND;TZID=CET:20260610T132000
DESCRIPTION:As the RISC-V software ecosystem achieves maturity for high-per
 formance computing\, the demand for production-ready\, competitive process
 or cores has reached a critical point. This presentation introduces the X2
 00\, our flagship RISC-V core\, which has completed its entire development
  cycle and is now ready for deployment. We provide a comprehensive overvie
 w of the X200's journey\, from its ambitious design goals to final GDS lay
 out. The session details its advanced multi-stage pipeline\, sophisticated
  memory subsystem\, and scalable multi-core interconnect fabric. We presen
 t a transparent competitive analysis\, share key benchmark results\, and r
 eveal detailed Power\, Performance\, and Area (PPA) data verified from the
  final layout. Attendees will gain a clear understanding of the X200's cap
 abilities and its readiness to power next-generation SoCs.
DTSTAMP:20260715T070248Z
LOCATION:Poster Island C
SUMMARY:From Architecture to GDS: Introducing the X200\, a Market-Ready\, H
 igh-Performance RISC-V Core - feixiaolong
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/MQJFNF/
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