IPECC, an open-source side-channel-resistant ECC hardware accelerator developed by the French national agency ANSSI, is integrated into the CVA6 RISC-V SoC and prototyped on a Genesys 2 (XC7K325T) FPGA. Using the libecc cryptographic library, we evaluate eight signature scheme/curve combinations in three configurations: software-only execution, hardware acceleration without countermeasures, and fully protected hardware acceleration. With all countermeasures active, IPECC reduces ECDSA P-256 signature latency from 1.13 s to 180 ms (a 6.3x speedup), reaching 7.8x for Schnorr-based schemes and scaling up to 9.1x for P-521. On the FPGA target, the countermeasure overhead varies drastically from +3% (hash-dominated EdDSA) to +279% (Schnorr-based schemes). We demonstrate that this variance is fundamentally driven by the physical True Random Number Generator (TRNG) latency and each protocol’s specific reliance on scalar multiplication. In its compact P-256 configuration, the accelerator occupies only 4.2% of the FPGA LUT fabric (3,602 LUTs, 12 DSP48E1). This platform provides a reproducible basis for benchmarking ECC acceleration and side-channel countermeasures on RISC-V SoCs.