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UID:pretalx-eu-summit-2026-QBSVKB@cfp.riscv-europe.org
DTSTART;TZID=CET:20260611T110000
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DESCRIPTION:Our contribution demonstrates how developers can easily run neu
 ral networks on RISC-V processors using our custom hardware accelerator Te
 traEdge.\nWe present a complete solution combining three components.\n\nFi
 rst\, we introduce TetraEdge\, a custom hardware SIMD accelerator.\nTetraE
 dge contains a four-stage pipeline design to accelerate 8-bit quantized CN
 Ns inference on 32-bit RISC-V processors.\nIn comparison to other hardware
  accelerators\, TetraEdge features an innovative automatic data reordering
  and min/max accumulation.\n\nSecond\, we extend the NeoRV32 open-source R
 ISC-V processor\,\nby two custom instructions to control TetraEdge without
  blocking the main processor.\nThe CPU continues other tasks while the acc
 elerator handles neural network operations.\nBy directly interfacing with 
 the CPU core's register file\, TetraEdge minimizes area\nand control compl
 exity\, enabling seamless integration into existing toolchains.\n\nFinally
 \, we combine both aforementioned contributions to the open-source framewo
 rk AIfES (Artificial Intelligence for Embedded Systems).\nAIfES is specifi
 cally designed to train and run neural networks directly on resource-const
 rained devices.\nIts modular software architecture enables the integration
  of user-specific hardware accelerators\, such as TetraEdge.\nAIfES reduce
 s software overhead significantly with up to 54\\% less memory usage and f
 aster execution for CNNs.
DTSTAMP:20260522T162344Z
LOCATION:Poster Island C
SUMMARY:Accelerating neural networks using SIMD ISA-Extension for RISC-V pr
 ocessor platforms: A complete toolflow - Alexander Zapp\, Carsten Rolfes
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/QBSVKB/
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