Compilers play a central role in unlocking the full performance potential of rapidly evolving RISC-V processors. In the practice of optimizing SPEC CPU 2006 and SPEC CPU 2017 using LLVM for RISC-V, a few compiler optimizations targeting RISC-V have been implemented, involving approaches that both enhance the effectiveness of individual optimization passes and refine how passes interact within the optimization pipeline.
This work introduces four such optimizations integrated into LLVM: (1) extending loop interchange to support loops containing reduction patterns, (2) enhancing loop strength reduction for nested loops, (3) eliminating unnecessary loop counters to unlock further optimizations such as loop unroll, and (4) refactoring multi-dimensional array accesses to enable subsequent redundant computation elimination. While motivated by RISC-V performance tuning, the proposed techniques can also benefit other architectures such as x86. Evaluated on SPEC CPU 2006 and SPEC CPU 2017, these improvements achieve performance gains ranging from 6\% to 54\% across Intel i9-11900K, SpacemiT Key Stone K1, and XiangShan KMHv3 platforms.

The RISC-V architecture has experienced rapid growth in recent years, evolving from an academic research project into a global ecosystem spanning industry, academia, and open-source communities. However, achieving competitive application performance across the diverse RISC-V microarchitectures requires a mature compiler infrastructure capable of realizing the performance potential of the underlying hardware. In this work, we present XSCC, a high-performance compiler built on LLVM 19.1.0, designed to meet industrial-grade performance demands while actively contributing to open-source ecosystem development. XSCC performs a systematic cross-architecture optimization analysis, distilling compiler insights from mature architectures into a cohesive set of optimizations for RISC-V, including enhanced loop transformations, memory access reordering, and microarchitecture-specific scheduling models. Four of these optimizations have been upstreamed to the LLVM project. Experimental evaluation demonstrates consistent improvements over baseline LLVM 19 and GCC 12, achieving up to 1.14x speedup on SPEC CPU 2006 FP on the simulated XiangShan KMHv3 and up to 1.30x speedup on SPEC CPU 2006 INT on commercial RISC-V hardware SpacemiT X60.