Petr Kourzanov
Having started personal journey in Uzbekistan, and professional career in Delft, Peter delved into SW engineering (at TU/d) towards streaming and multimedia systems for CE (architecture & infrastructure group at Philips Research, NatLab). He developed a passion for fun PLs such as Icon, Scheme and Julia, which he applied in projects such a simulation modeling, virtual prototype environments and a joint project on SDR with Nokia. Dataflow compiler & middleware project got him further into the DSP algorithms and radio & radar transceivers - focus of the work at NXP Semiconductors for more than 10 years, resulting in IPs for, e.g., SAF85xx made with Julia and RoadLink SAF5400 made with SystemC and HLS. At IMEC since 2022, he focuses on SW/HW interfaces, simulation infra and on micro-arch modeling for RISC-V and CMOS2.0. Since 2019 he consults in efficient networking stack simulation, automation and nano-kernels such as Zephyr.
Session
Open-source hardware is booming. To prevent fragmentation, encourage collaboration and reuse we propose the RISC-V to join forces with Reproducible Builds communities and concentrate innovation potential where its needed most: creation of new micro-architectures, IPs and their integration into new SoCs and applications. To facilitate this goal, we chose Guix, a rigorous solution for reproducible software artefacts. We apply it to dependency management & reproducibility problems in open-source hardware and show the validity of the approach, taking CVA6 as a running example. The end result - a fully reproducible collection of packaged tests, emulation, simulation and cycle-accurate models - shows a promising workflow that could (in future) scale to support larger RISC-V community with reusable software & hardware components for next-generation platforms.