RISC-V provides complex platform-level specifications, such as the RISC-V IOMMU, in addition to the core-level ISA to support a complete open computing platform. The RISC-V IOMMU delves into intricate hardware-software interactions, page table formats, command and fault queue handling, and multi-stage address translations that are as critical to system correctness but significantly harder to validate.
An essential part of verifying the IOMMU involves executing real-world scenarios as would be presented via Linux. However, setting up a full SoC-level environment to run Linux sequences is time-consuming and resource-intensive. As a result, critical IOMMU interactions are often validated too late or not at all.

We have developed a programmable device model that permits Linux testing of RISC-V IOMMU RTL without requiring PCIe or DMA-capable devices to be integrated into the design under test.
The device model has been pivotal in creating an emulation-friendly subsystem-level environment that integrates high-performance RISC-V cores (TT-Ascalon) with RISC-V IOMMU.
The subsystem runs Linux as the primary stimulus source, reusing the upstream kernel IOMMU driver to exercise the IOMMU implementation against the RISC-V specification with complex and realistic scenarios.

We will present the design and operation of this device model, the subsystem environment and related software, and shall share our findings, including how it enabled us to quickly uncover corner-case bugs in our IOMMU RTL and its software drivers, thereby complementing traditional IP-level validation approaches.