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UID:pretalx-eu-summit-2026-SXGTPT@cfp.riscv-europe.org
DTSTART;TZID=CET:20260609T141000
DTEND;TZID=CET:20260609T142000
DESCRIPTION:Post-Quantum Cryptography (PQC) is moving from algorithm select
 ion to deployment\, where performance\, energy\, and portability are key c
 onstraints\, especially on embedded and IoT-class processors. Many PQC sch
 emes stress general-purpose cores with large arithmetic workloads and heav
 y memory traffic. Instruction-set extensions (ISE) offer a practical middl
 e ground: they speed up dominant kernels while preserving programmability.
 \nIn this context\, we target post-quantum digital signatures\, which rema
 in under active evaluation\, as reflected by NIST's 2023 call for addition
 al schemes. We focus on CROSS\, a code-based signature built from zero-kno
 wledge proofs and the Restricted Syndrome Decoding Problem\, and present C
 IRCE: a RISC-V–integrated extension connected through the Core-V eXtensi
 on Interface (CV-X-IF). CIRCE supports both R-SDP and R-SDP(G)\, runs acro
 ss all official parameter sets without hardware retuning\, and achieves an
  average 2x speed-up on a Zynq UltraScale+ FPGA with an ultra-compact foot
 print (down to 800 LUTs / 100 FFs).
DTSTAMP:20260522T162455Z
LOCATION:Poster Island B
SUMMARY:CIRCE: CROSS Integrated RISC-V Cryptographic Extension - Valeria Pi
 scopo\, aledolme
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/SXGTPT/
END:VEVENT
BEGIN:VEVENT
UID:pretalx-eu-summit-2026-ACRS3G@cfp.riscv-europe.org
DTSTART;TZID=CET:20260609T155000
DTEND;TZID=CET:20260609T160000
DESCRIPTION:As the NIST Lightweight Cryptography (LWC) standard\, ASCON is 
 pivotal for securing IoT ecosystems. This work presents CHIMERA\, a multip
 urpose cryptographic engine for RISC-V\, supporting AEAD and Hashing. We p
 ropose two architectural paradigms integrated via the Core-V eXtension Int
 erface (CV-X-IF): a high-performance Complete Round (CR) version utilizing
  a state-register bank\, and a minimalist Bitwise Rotation Unit (BRU) vers
 ion focusing on Instruction Set Extensions (ISE). Our designs suit through
 put-critical workloads\, delivering up to 6x speed-up\, as well as footpri
 nt-constrained deployments on ASIC and FPGA.
DTSTAMP:20260522T162455Z
LOCATION:Poster Island B
SUMMARY:CHIMERA: Cryptographic Hardware for Integrated Multipurpose Engine 
 on RISC-V with ASCON - Enrico Manfredi\, aledolme\, Valeria Piscopo
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/ACRS3G/
END:VEVENT
BEGIN:VEVENT
UID:pretalx-eu-summit-2026-ZZQYRH@cfp.riscv-europe.org
DTSTART;TZID=CET:20260609T160000
DTEND;TZID=CET:20260609T161000
DESCRIPTION:This paper introduces HORCRUX\, an open RISC-V instruction set 
 extension for post-quantum cryptography (PQC). A modular PQ-ALU\, integrat
 ed through the Core-V eXtension Interface (CV-X-IF) accelerates the core k
 ernels shared by hash-\, lattice-\, and code-based schemes\, including Kec
 cak processing\, sampling\, modular/polynomial arithmetic\, finite-field o
 perations\, and coefficient compression. The design targets NIST-standardi
 zed algorithms (ML-KEM\, ML-DSA\, SLH-DSA\, HQC) and additional candidates
  under evaluation. We release the complete hardware/software stack as open
  source and report 65 nm ASIC post-synthesis results: with a compact footp
 rint of ~26.3 kGE and energy savings up to 99.5%\, the extension provides 
 a practical route to energy-efficient PQC on RISC-V with minimal integrati
 on effort.
DTSTAMP:20260522T162455Z
LOCATION:Poster Island B
SUMMARY:HORCRUX: a Post-Quantum Cryptography Instruction Set Extension - Va
 leria Piscopo\, aledolme
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/ZZQYRH/
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