Spandan Das
Spandan Das is a Ph.D. student at the Group of Computer Architecture in University of Bremen, under the supervision of Professor Dr. Christoph Lüth and Prof. Dr. Rolf Drechsler. He received his B.Sc. and M.Sc. degrees in Mathematics from Indian Institute of Science Education and Research Kolkata, India, and M.Tech. in Computer Science from Indian Statistical Institute Kolkata, India. His Ph.D. work concerns designing hardware-based security and related benchmarks for resource-constrained IoT devices.
Session
The adoption of capability-based architectures such as Capability Hardware Enhanced RISC Instructions (CHERI) in constrained RISC-V systems raises open questions regarding performance overheads, verification complexity, and practical evaluation methodologies. Virtual prototyping provides an effective means to explore these questions early in the design process, before committing to Register-Transfer Level (RTL) implementations. In this paper, we present a CHERI-enabled RISC-V Virtual Prototype (VP) targeting constrained embedded systems and demonstrate its use for early architectural evaluation. We describe VP-based verification workflows for both software and hardware and report early performance insights focusing on CHERI tagged memory management. Our experiences highlight the benefits of VPs for guiding CHERI adoption decisions and identify practical challenges, including the need for lightweight benchmarks suitable for constrained environments.