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UID:pretalx-eu-summit-2026-RGDVRL@cfp.riscv-europe.org
DTSTART;TZID=CET:20260609T141000
DTEND;TZID=CET:20260609T142000
DESCRIPTION:As RISC-V moves from experimental silicon to mass-market indust
 rial applications\, the availability of proven\, safety-certified Real-Tim
 e Operating Systems (RTOS) is a key enabler for adoption. Eclipse ThreadX 
 (formerly Azure RTOS) has long been a cornerstone of the embedded industry
 . Yet\, its immature support for the RISC-V ISA\, particularly 64-bit impl
 ementations\, remained a barrier for high-performance adoption.\n\nIn this
  session\, you will learn how 10xEngineers\, in collaboration with the Ecl
 ipse ThreadX project team\, brought first-class RISC-V support to the Thre
 adX kernel. You will go on a deep dive into the architectural challenges o
 f porting the kernel's core components to both RV32 and RV64\, including c
 ontext switching\, interrupt nesting\, and timer management tailored for t
 he RISC-V privileged architecture. You will also explore the practical ena
 blement of this port on the SpacemiT K1 SoC (Banana Pi BPI-F3)\, bridging 
 the gap between virtual prototyping in QEMU and physical hardware deployme
 nt. Finally\, you will gain insights into the low-level kernel modificatio
 ns required for RISC-V compliance and discover a roadmap for deploying Thr
 eadX in the next generation of RISC-V embedded systems.
DTSTAMP:20260522T162439Z
LOCATION:Poster Island D
SUMMARY:Beyond the Basics: Elevating Eclipse ThreadX to a First-Class RTOS 
 for RISC-V - Frédéric Desbiens\, Akif Ejaz
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/RGDVRL/
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UID:pretalx-eu-summit-2026-DMVSJ8@cfp.riscv-europe.org
DTSTART;TZID=CET:20260609T161000
DTEND;TZID=CET:20260609T162000
DESCRIPTION:The RISC-V instruction set architecture (ISA) has seen rapid ad
 option over the past few years. Despite\nthis growth\, the software ecosys
 tem remains a major challenge to broader adoption. In contrast to x86 and 
 ARM platforms\, where precompiled binaries are widely available\, RISC-V d
 evelopers often face a significant software availability gap. Consequently
 \, many packages\, libraries\, or applications must be built from source\,
  requiring substantial expertise in build systems and target architectures
 . This process is largely manual and time-consuming\, creating a significa
 nt barrier to widespread adoption of the RISC-V. To address this critical 
 gap\, this paper presents ATESOR\, a multi-stage LLM-based framework for a
 utonomous RISC-V software porting. The framework uses large language model
 s to plan build requirements\, compile packages\, debug failures\, and tes
 t generated binaries in RISC-V sandboxed environments. ATESOR supports bot
 h containerized RISC-V environment and native execution on RISC-V hardware
  such as the Banana Pi BPI-F3 and Milk-V Pioneer\, provided by Cloud-V. AT
 ESOR is trained on an internal dataset of more than 500 manually ported pa
 ckages spanning build systems including CMake\, Make\, Ninja\, and Go. For
  100 CMake and Go-based packages\, ATESOR demonstrated a 80% successful po
 rting rate and experiment completed in approximately 1.5 hours\, correspon
 ding to an average porting time of about 54 seconds per package.
DTSTAMP:20260522T162439Z
LOCATION:Poster Island C
SUMMARY:ATESOR: A Multi-Stage LLM-based Framework for Autonomous RISC-V Sof
 tware Porting - Akif Ejaz
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/DMVSJ8/
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