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UID:pretalx-eu-summit-2026-88TJXG@cfp.riscv-europe.org
DTSTART;TZID=CET:20260611T130000
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DESCRIPTION:Data integrity and fault tolerance are prerequisites for RISC-V
  adoption in enterprise server environments\, relying heavily on Cyclic Re
 dundancy Check (CRC) and Erasure Coding (EC) for storage reliability and n
 etwork transmission. Currently\, the RISC-V ISA lacks the dedicated hardwa
 re acceleration found in mature architectures such as x86\, leading to sig
 nificant overhead in implementations. We propose novel ISA extensions to b
 ridge this gap: a fused carry-less multiply-add instruction for CRC foldin
 g achieving up to 4x speedup\, and a specialized GF(2^8) multiply-accumula
 te instruction for EC delivering 4x throughput gains over vectorized basel
 ines. Evaluation confirms that these extensions significantly enhance data
  path efficiency\, positioning RISC-V as a competitive architecture for re
 liable\, high-performance storage and networking systems.
DTSTAMP:20260522T162519Z
LOCATION:Poster Island A
SUMMARY:High-Performance CRC/EC Acceleration for RISC-V Server Storage via 
 Novel ISA Extensions - Zhanheng Yang\, Fengrui Sun
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/88TJXG/
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