Ashley Stevens
Ashley Stevens is Director of Product Management and Marketing at Arteris responsible for coherent NoCs and die-2-die interconnects. He has over 35 years of industry experience and previously held roles at Arm, SiFive and Acorn Computers. He holds 11 granted patents and has a degree in Computer Engineering from Queen Mary, University of London.
Session
To enhance processor performance on HPC and AI workloads, the RISC-V Vector Extension (RVV) was ratified by RISC-V International in 2021. Vector processing enables data parallelism by operating on vectors rather than scalars, which studies have shown can improve performance on vectorized workloads by up to eight times or more on some workloads, significantly increasing memory bandwidth requirements compared with scalar processors. The proposed RISC-V Matrix Extensions further multiply the challenges, placing even greater demands on the memory subsystem. This increased data throughput requires architects to re-evaluate their long-held assumptions about SoC architecture. While many studies focus on the software implications of vector and matrix extensions, this paper explores the challenges and evaluates possible solutions for performant and power-efficient, optimal SoC hardware architectures.