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UID:pretalx-eu-summit-2026-PRQ9ES@cfp.riscv-europe.org
DTSTART;TZID=CET:20260611T103000
DTEND;TZID=CET:20260611T104000
DESCRIPTION:To enhance processor performance on HPC and AI workloads\, the 
 RISC-V Vector Extension (RVV) was ratified by RISC-V International in 2021
 . Vector processing enables data parallelism by operating on vectors rathe
 r than scalars\, which studies have shown can improve performance on vecto
 rized workloads by up to eight times or more on some workloads\, significa
 ntly increasing memory bandwidth requirements compared with scalar process
 ors. The proposed RISC-V Matrix Extensions further multiply the challenges
 \, placing even greater demands on the memory subsystem. This increased da
 ta throughput requires architects to re-evaluate their long-held assumptio
 ns about SoC architecture. While many studies focus on the software implic
 ations of vector and matrix extensions\, this paper explores the challenge
 s and evaluates possible solutions for performant and power-efficient\, op
 timal SoC hardware architectures.
DTSTAMP:20260715T070247Z
LOCATION:Poster Island B
SUMMARY:NoC and Memory Subsystems for AI Employing RISC-V Processors with V
 ector or Matrix Extensions - Ashley Stevens
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/PRQ9ES/
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