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UID:pretalx-eu-summit-2026-V33F9K@cfp.riscv-europe.org
DTSTART;TZID=CET:20260611T141000
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DESCRIPTION:The transition toward centralized automotive computing platform
 s demands scalable\, high-performance\, and energy-efficient AI accelerati
 on tightly integrated with open instruction set architectures. Within the 
 European Chips Joint Undertaking framework\, the [PROJECT NAME] project de
 velops a next-generation automotive hardware platform based on RISC-V tech
 nology.\nThis paper explores three hardware acceleration paradigms applica
 ble to RISC-V-based automotive systems: (i) memory-mapped monolithic accel
 erators\, (ii) custom ISA extensions tightly coupled to the processor pipe
 line\, and (iii) Near-Memory Computing (NMC) architectures. We present an 
 ongoing comparative study evaluating their applicability to representative
  automotive AI kernels\, including conventional neural networks (CNNs\, ML
 Ps)\, data-driven battery models\, and emerging Spiking Neural Networks (S
 NNs).\nWhile all paradigms provide workload-dependent performance benefits
 \, preliminary architectural analysis suggests that Near-Memory Computing 
 offers superior scalability and energy efficiency for memory-bound AI work
 loads. Complementing the hardware effort\, we develop a software ecosystem
  leveraging MLIR-based compilation flows to efficiently map both conventio
 nal and neuromorphic models onto heterogeneous RISC-V accelerators.
DTSTAMP:20260522T162438Z
LOCATION:Poster Island B
SUMMARY:Exploring AI Acceleration Paradigms for Automotive RISC-V Platforms
  - DAVID ALBACETE SEGURA\, Anestis Athanasiadis
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/V33F9K/
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