The use of open-source stacks with the Open~RAN (Radio Access Network) architecture has been predominantly restricted to x86 and ARM architectures. This work presents the first successful porting of the srsRAN Project to RISC-V, targeting the low-cost Banana Pi BPI-F3 (SpacemiT K1 SoC) board. We describe the cross-compilation toolchain, the removal of AVX/NEON dependencies in favour of a scalar C fallback, and a preliminary performance evaluation across two 5G NR FDD scenarios. Profiling with Linux perf identifies key data-parallel physical layer (PHY) bottlenecks, establishing primary targets for RVV 1.0 vectorisation. Results show that RISC-V offers promising real-time MIMO performance for a single user, even with a scalar fallback, suggesting that vectorisation will elevate it to highly competitive levels.

In this paper, we present the results of the XXXXXXXX project, in which a fully open-source, parametrizable low-power floating-point unit (FPU) under HUB format has been designed and validated. This unit, implemented in SystemVerilog, supports addition, subtraction, multiplication, division, square root, and Fused Multiply-Add (FMA) operations under HUB format. This FPU has been exhaustively tested through simulation and FPGA implementations. Moreover, it has been integrated with some RISC-V cores and validated using several test benches. The development is complemented by a compiler environment that enables native FPHUB arithmetic for C and C++ programs. The proposed unit achieves a roughly 60\% reduction in area and power consumption compared with a classic IEEE FPU implementation.