BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//pretalx//cfp.riscv-europe.org//eu-summit-2026//speaker//S3CLBQ
BEGIN:VTIMEZONE
TZID:CET
BEGIN:STANDARD
DTSTART:20001029T040000
RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=10
TZNAME:CET
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
END:STANDARD
BEGIN:DAYLIGHT
DTSTART:20000326T030000
RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=3
TZNAME:CEST
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
END:DAYLIGHT
END:VTIMEZONE
BEGIN:VEVENT
UID:pretalx-eu-summit-2026-9G3V9G@cfp.riscv-europe.org
DTSTART;TZID=CET:20260609T112000
DTEND;TZID=CET:20260609T113000
DESCRIPTION:The use of open-source stacks with the Open~RAN (Radio Access N
 etwork) architecture has been predominantly restricted to x86 and ARM arch
 itectures. This work presents the first successful porting of the srsRAN P
 roject to RISC-V\, targeting the low-cost Banana Pi BPI-F3 (SpacemiT K1 So
 C)  board. We describe the cross-compilation toolchain\, the removal of AV
 X/NEON dependencies in favour of a scalar C fallback\, and a preliminary p
 erformance evaluation across two 5G NR FDD scenarios. Profiling with Linux
  perf identifies key data-parallel physical layer (PHY) bottlenecks\, esta
 blishing primary targets for RVV 1.0 vectorisation. Results show that RISC
 -V offers promising real-time MIMO performance for a single user\, even wi
 th a scalar fallback\, suggesting that vectorisation will elevate it to hi
 ghly competitive levels.
DTSTAMP:20260522T162354Z
LOCATION:Poster Island D
SUMMARY:Implementation of Open RAN software in a RISC-V platform - Javier H
 ormigo
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/9G3V9G/
END:VEVENT
BEGIN:VEVENT
UID:pretalx-eu-summit-2026-PYSBZM@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T142000
DTEND;TZID=CET:20260610T143000
DESCRIPTION:In this paper\, we present the results of the XXXXXXXX project\
 , in which a fully open-source\, parametrizable low-power floating-point u
 nit (FPU) under HUB format has been designed and validated. This unit\, im
 plemented in SystemVerilog\, supports addition\, subtraction\, multiplicat
 ion\, division\, square root\, and Fused Multiply-Add (FMA) operations und
 er HUB format. This FPU has been exhaustively tested through simulation an
 d FPGA implementations. Moreover\, it has been integrated with some RISC-V
  cores and validated using several test benches. The development is comple
 mented by a compiler environment that enables native FPHUB arithmetic for 
 C and C++ programs. The proposed unit achieves a roughly 60\\% reduction i
 n area and power consumption compared with a classic IEEE FPU implementati
 on.
DTSTAMP:20260522T162354Z
LOCATION:Poster Island D
SUMMARY:Low-power Floating Point Unit for RISC-V Processors using FPHUB for
 mat - Javier Hormigo
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/PYSBZM/
END:VEVENT
END:VCALENDAR