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UID:pretalx-eu-summit-2026-ZFT38M@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T140000
DTEND;TZID=CET:20260610T141000
DESCRIPTION:Domain-Specific architectures with accelerators for machine lea
 rning and signal processing require efficient bulk data movement and high-
 bandwidth access to large datasets. Such capabilities are often absent fro
 m minimal open-source microcontrollers (MCUs). \nWe present HyperCroc\, an
  extension to the end-to-end open-source RISC-V Croc system-on-chip (SoC) 
 integrating a silicon-proven HyperBus controller for off-chip DRAM and Fla
 sh memory access and a DMA engine\, providing a practical MCU-class platfo
 rm with streamlined plug-in support for domain-specific acceleration. Hype
 rBus offers a low-pin-count PSDRAM interface at up to 400 MB/s\, enabling 
 bandwidth-scaled dataset access\, while the DMA engine enables autonomous\
 , high-throughput transfers without CPU intervention. HyperCroc preserves 
 Croc’s open-source synthesis and physical implementation flow targeting 
 IHP’s open 130 nm process design kit (PDK)\; the full chip can be implem
 ented in under one hour on a consumer-grade workstation. \nWe further repo
 rt first silicon measurements from MLEM\, the first Croc tapeout\, confirm
 ing that the silicon is fully functional at 72 MHz @ 1.2 V and validating 
 the end-to-end flow.
DTSTAMP:20260715T065854Z
LOCATION:Poster Island C
SUMMARY:HyperCroc: Open-Source RISC-V MCU with Plug-In Interface for Domain
 -Specific Accelerators - Philippe Sauter
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/ZFT38M/
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UID:pretalx-eu-summit-2026-PTWGKY@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T160000
DTEND;TZID=CET:20260610T161000
DESCRIPTION:Recent announcements have shown the viability of end-to-end ope
 n-source (OS) Linux-capable RISC-V systems on chip (SoCs). However\, pract
 ical application and software development platforms require efficient non-
 volatile storage\, which is not adequately served by common SPI-based inte
 rfaces due to their limited throughput. Secure Digital (SD) cards are the 
 de facto standard storage medium for embedded Linux systems\; efficient SD
  host controller (SDHC) integration is thus essential for open-source RISC
 -V platforms. \nWe present an OS SD host controller interface (SDHCI) peri
 pheral integrated into the end-to-end OS Cheshire RISC-V SoC platform. The
  controller and its software stack are designed with full awareness of CVA
 6’s memory system and Linux driver behavior\; during evaluation\, we ide
 ntify a significant performance bottleneck caused by the RISC-V memory mod
 el and CVA6’s implementation of the fence instruction\, which flushes th
 e pipeline and data cache on memory-mapped register accesses when cache ma
 nagement operations (CMOs) are unavailable. By customizing the driver’s 
 register access paths and avoiding unnecessary fences\, we substantially r
 educed this overhead. Our fully OS controller achieves up to 11.1 MB/s thr
 oughput\, approaching the 12.5 MB/s limit of the SD interface and providin
 g up to 6.5 times the throughput of SPI-based storage.
DTSTAMP:20260715T065854Z
LOCATION:Poster Island D
SUMMARY:Implementing and Optimizing an Open-Source SD-card Host Controller 
 for RISC-V SoCs - Philippe Sauter
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/PTWGKY/
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