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UID:pretalx-eu-summit-2026-RTYDA8@cfp.riscv-europe.org
DTSTART;TZID=CET:20260611T133000
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DESCRIPTION:We present an end-to-end framework for the automatic generation
  of custom RISC-V instruction-subset processors (RISSPs) tailored to machi
 ne learning (ML) inference. Building on the RISSP methodology\, our fully 
 automated flow accepts model hyperparameters and a target dataset\, perfor
 ms offline training\, and generates the complete inference implementation 
 together with all deployment artifacts for the target device. The resultin
 g inference code then drives the RISSP generation\, synthesising a custom 
 processor that implements only the RISC-V instructions used by the applica
 tion. By co-optimizing software and hardware within a tightly integrated c
 o-design toolchain\, the combined flow reduces ISA footprint and design co
 mplexity\, enabling smaller and more energy-efficient processors for ML wo
 rkloads at the edge.
DTSTAMP:20260522T162444Z
LOCATION:Poster Island B
SUMMARY:RISC-V Instruction-Subset Processors for Extreme Edge Machine Learn
 ing. - Konstantinos Iordanou\, Shengyu Duan
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/RTYDA8/
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