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UID:pretalx-eu-summit-2026-YAEZRU@cfp.riscv-europe.org
DTSTART;TZID=CET:20260609T135000
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DESCRIPTION:RISC-V is rapidly emerging as an open and extensible ISA\, yet 
 its adoption in desktop and server environments remains constrained by the
  dominance of the x86-64 software ecosystem. Dynamic binary translation (D
 BT) provides a practical mechanism for executing legacy x86-64 binaries on
  RISC-V without source code\, but purely software-based DBT often incurs s
 ubstantial overhead. In this work\, we investigate a hardware/software co-
 designed approach for user-level x64-to-RV64 translation. We begin with a 
 fine-grained characterization of runtime instruction behavior from SPEC CP
 U 2017 benchmarks\, and extract micro-operation (μop) information for dif
 ferent instruction variants on a representative x86 microarchitecture. By 
 correlating dynamic execution profiles with μop-level complexity\, we int
 roduce a quantitative model of semantic inflation\, which exposes the sema
 ntic gap introduced by cross-ISA translation by discounting the inherent e
 xecution complexity of CISC instructions. This model enables us to systema
 tically identify instruction variants that exhibit disproportionate expans
 ion and reveals the underlying causes of this bloat. Based on these insigh
 ts\, we propose targeted hardware extensions to mitigate translation overh
 ead. We implement the proposed approach in a Box64-based prototype and eva
 luate it through QEMU-based simulation. Experimental results demonstrate a
  significant reduction in the number of translated instructions\, indicati
 ng a practical path toward near-native cross-ISA execution efficiency.
DTSTAMP:20260522T162745Z
LOCATION:Poster Island D
SUMMARY:Revisiting x86-64 to RISC-V Binary Translation: A Hardware/Software
  Co-Design Path - Xieyuan Wu
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/YAEZRU/
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