The rapid expansion of the RISC-V ecosystem has led to an increasing number of open hardware projects hosted on collaborative platforms such as GitHub. While modern software development benefits from mature continuous integration and continuous deployment (CI/CD) methodologies, equivalent automated verification infrastructure remains limited for hardware design. In particular, formal verification tools such as logic equivalence checking (LEC) remain largely restricted to proprietary EDA solutions.
This work explores the use of lightweight open-source EDA tools as scalable verification agents for open hardware development workflows. We present an open-source logic equivalence checking tool designed to operate efficiently within CI environments for RISC-V projects. Built on a high-performance C++ infrastructure for netlist representation and analysis, the tool enables rapid equivalence verification between different RTL transformations and synthesized netlists. Experimental results on open RISC-V designs demonstrate that automated equivalence checks can be integrated into CI pipelines with execution times compatible with typical pull request validation workflows. This approach provides a practical first verification gate for open hardware repositories before deeper sign-off verification using commercial tools.