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UID:pretalx-eu-summit-2026-WLDTDU@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T113000
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DESCRIPTION:Smart glasses must run multiple demanding applications—speech
  enhancement\, eye tracking\, and automatic speech recognition—simultane
 ously within tens of milliwatts of power budget. This poses a significant 
 challenge for platforms constrained by milliampere-hour batteries and gram
 -scale form factors.\nOpen hardware ecosystems\, and RISC-V in particular\
 , have proven invaluable. Rather than a contribution target\, RISC-V provi
 des a foundation to build on. Recent industrial and academic efforts have 
 produced rigorously validated\, ultra-low-power microarchitectures and ext
 ensive open knowledge that significantly lowers the barrier to custom sili
 con for teams whose expertise lies outside traditional semiconductor IP de
 velopment.\nThe second key challenge is on-device ML inference in a field 
 where model architectures evolve faster than fixed-function accelerators. 
 Hyper-specialized NPUs risk obsolescence before shipping. The solution is 
 heterogeneous SoCs: systems where dedicated NPUs handle heavy-lifting for 
 characterized inference workloads\, tightly coupled with programmable RISC
 -V cores for pre/post processing and new operations.\nCrucially\, RISC-V c
 ores are extensible. Their ISA can be extended with custom instructions to
  efficiently cover emerging operators without full hardware redesigns—av
 oiding the obsolescence problem entirely.\nThis talk offers a high-level p
 erspective on how a product-driven company approaches custom silicon for s
 mart eyewear\, and why RISC-V sits at the center of that strategy.
DTSTAMP:20260715T065811Z
LOCATION:Plenary
SUMMARY:From Eyewear to Silicon: RISC-V for Low-Power AI in Next-Generation
  Smart Glasses - Marco Fariselli
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/WLDTDU/
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