Verification has become one of the most time-consuming stages in modern high-performance processor development. Co-simulation compares the Design Under Test (DUT) against a reference model (REF) at instruction granularity, providing strong debuggability, but existing software-based solutions are limited to KHz-level speeds and cannot meet industrial-scale verification demands. FPGA platforms can accelerate processor simulation to tens of MHz; however, massive and frequent hardware-software communication between the FPGA-hosted DUT and software REF still constrains co-simulation throughput.

We present DiffTest-H, an FPGA-accelerated co-simulation framework for industrial-scale RISC-V processor verification. By exploiting the structural, ordering, and behavioral characteristics of verification data, DiffTest-H optimizes communication through compression and packaging while preserving instruction-level comparison and debugging capability. It reduces communication overhead by up to 99.7% with 3.2% additional area overhead on Xilinx VU19P, achieving co-simulation speeds beyond 10 MHz and enabling faster verification iteration.

DiffTest-H has been deployed to verify XiangShan, a high-performance out-of-order RISC-V processor, covering interrupts, memory hierarchy behaviors, vector extensions, and virtualization. Across FPGA and emulator platforms, it has helped uncover more than 151 complex bugs in XiangShan, demonstrating its effectiveness for large-scale industrial processor verification.