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UID:pretalx-eu-summit-2026-QUEMGA@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T105500
DTEND;TZID=CET:20260610T110500
DESCRIPTION:Verification has become one of the most time-consuming stages i
 n modern high-performance processor development. Co-simulation compares th
 e Design Under Test (DUT) against a reference model (REF) at instruction g
 ranularity\, providing strong debuggability\, but existing software-based 
 solutions are limited to KHz-level speeds and cannot meet industrial-scale
  verification demands. FPGA platforms can accelerate processor simulation 
 to tens of MHz\; however\, massive and frequent hardware-software communic
 ation between the FPGA-hosted DUT and software REF still constrains co-sim
 ulation throughput.\n\nWe present DiffTest-H\, an FPGA-accelerated co-simu
 lation framework for industrial-scale RISC-V processor verification. By ex
 ploiting the structural\, ordering\, and behavioral characteristics of ver
 ification data\, DiffTest-H optimizes communication through compression an
 d packaging while preserving instruction-level comparison and debugging ca
 pability. It reduces communication overhead by up to 99.7% with 3.2% addit
 ional area overhead on Xilinx VU19P\, achieving co-simulation speeds beyon
 d 10 MHz and enabling faster verification iteration.\n\nDiffTest-H has bee
 n deployed to verify XiangShan\, a high-performance out-of-order RISC-V pr
 ocessor\, covering interrupts\, memory hierarchy behaviors\, vector extens
 ions\, and virtualization. Across FPGA and emulator platforms\, it has hel
 ped uncover more than 151 complex bugs in XiangShan\, demonstrating its ef
 fectiveness for large-scale industrial processor verification.
DTSTAMP:20260715T065500Z
LOCATION:Demo Theater
SUMMARY:DiffTest-H: FPGA-Accelerated RISC-V Co-simulation Verification Beyo
 nd 10 MHz - XU AN\, Yinan Xu
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/QUEMGA/
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