The verification of integrated systems traditionally relies on detailed Register Transfer Level (RTL) simulations to ensure functional correctness before hardware implementation. While RTL simulation provides cycle-accurate behavior and can even achieve event-level precision when combinational delays are modeled, it suffers from extremely long execution times. Simulating complex software workloads such as booting an operating system may require several days of simulation time.
Instruction Set Simulators (ISS) provide a faster alternative for software execution. In the RISC-V ecosystem, Spike is the reference ISS and can achieve simulation speeds several orders of magnitude faster than equivalent RTL processor models. However, replacing the processor RTL model with an ISS introduces temporal discrepancies that may affect the accuracy of system-level simulations. This work presents Spike-RTL, a HW/SW co-simulation framework that integrates the Spike ISS with RTL models of the remaining hardware components. The tool supports both Verilog simulation and C/SystemC HW models (e.g. generated using Verilator). Experimental results show simulation speedups of up to 40× compared to Verilog simulation and 4× compared to Verilator, while maintaining timing errors on the order of 10%. The framework also introduces configurable timing models for instruction execution, cache miss latency integration, and variable-granularity synchronization mechanisms between ISS and RTL components.