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UID:pretalx-eu-summit-2026-FYCK9P@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T105000
DTEND;TZID=CET:20260610T110000
DESCRIPTION:The verification of integrated systems traditionally relies on 
 detailed Register Transfer Level (RTL) simulations to ensure functional co
 rrectness before hardware implementation. While RTL simulation provides cy
 cle-accurate behavior and can even achieve event-level precision when comb
 inational delays are modeled\, it suffers from extremely long execution ti
 mes. Simulating complex software workloads such as booting an operating sy
 stem may require several days of simulation time.\nInstruction Set Simulat
 ors (ISS) provide a faster alternative for software execution. In the RISC
 -V ecosystem\, Spike is the reference ISS and can achieve simulation speed
 s several orders of magnitude faster than equivalent RTL processor models.
  However\, replacing the processor RTL model with an ISS introduces tempor
 al discrepancies that may affect the accuracy of system-level simulations.
  This work presents Spike-RTL\, a HW/SW co-simulation framework that integ
 rates the Spike ISS with RTL models of the remaining hardware components. 
 The tool supports both Verilog simulation and C/SystemC HW models (e.g. ge
 nerated using Verilator). Experimental results show simulation speedups of
  up to 40× compared to Verilog simulation and 4× compared to Verilator\,
  while maintaining timing errors on the order of 10%. The framework also i
 ntroduces configurable timing models for instruction execution\, cache mis
 s latency integration\, and variable-granularity synchronization mechanism
 s between ISS and RTL components.
DTSTAMP:20260522T162518Z
LOCATION:Poster Island A
SUMMARY:Spike-RTL: Two technologies for fast and accurate SW-RTL co-simulat
 ion - Eugenio Villar
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/FYCK9P/
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