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UID:pretalx-eu-summit-2026-YQDVJU@cfp.riscv-europe.org
DTSTART;TZID=CET:20260609T130000
DTEND;TZID=CET:20260609T133000
DESCRIPTION:Post-Quantum Cryptography is becoming a key building block for 
 future secure systems\, as quantum computers threaten widely deployed publ
 ic-key cryptographic algorithms. In response\, the NIST standardization pr
 ocess has selected new quantum-resistant schemes\, among which ML-KEM play
 s a central role for key establishment. Deploying these algorithms efficie
 ntly on embedded processors is therefore a critical step toward practical 
 adoption\, particularly because embedded systems face strict constraints i
 n terms of computational resources\, memory footprint\, and energy consump
 tion. At the same time\, they are more exposed to physical threats\, makin
 g resistance to side-channel attacks a key requirement. These constraints 
 make RISC-V especially attractive: its open instruction set and extensibil
 ity allow experimentation with software optimizations as well as hardware 
 acceleration for PQC. To explore these aspects\, CEA has developed VASCO3\
 , a 22 nm ASIC chip designed to experimentally evaluate PQC implementation
 s and side-channel countermeasures directly on silicon. The chip integrate
 s a RISC-V–based System-on-Chip (SoC) together with several ML-KEM hardw
 are accelerators\, enabling the study of different hardware/software parti
 tioning strategies around an embedded RISC-V CPU. In this demonstration\, 
 we present a comprehensive exploration of ML-KEM. We first showcase a pure
  software implementation running on the RISC-V\, then progressively introd
 uce hardware acceleration and a fully dedicated ML-KEM accelerator. We als
 o demonstrate protected implementations based on first-order masking\, inc
 luding a masked software version and a masked hardware-assisted design.
DTSTAMP:20260522T162441Z
LOCATION:Devzone
SUMMARY:ML-KEM on a 22 nm ASIC: Protected\, Unprotected\, and Hardware-Ac
 celerated Implementations - Stefano Di Matteo\, Emanuele Valea
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/YQDVJU/
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UID:pretalx-eu-summit-2026-PB9JGQ@cfp.riscv-europe.org
DTSTART;TZID=CET:20260609T135000
DTEND;TZID=CET:20260609T140000
DESCRIPTION:This paper provides a quantitative analysis of the costs and be
 nefits of integrating a dedicated hardware accelerator for the Post Quantu
 m Cryptography (PQC) algorithm ML-KEM into a 32-bit RISC-V SoC. We compare
  a software-only implementation on the CV32E40P core against a full-hardwa
 re datapath offloading the entire algorithm. We implemented the system on 
 a 22 nm ASIC chip\, and we measured the results: the dedicated hardware ac
 hieves a 139x speed-up over the software baseline. This performance gain r
 equires an area overhead of 301 kGE\, representing only a 6% increase in t
 he total SoC silicon footprint. This study provides a data-driven assessme
 nt of the silicon-to-latency trade-off for Post-Quantum Cryptography (PQC)
  in resource-constrained RISC-V systems.
DTSTAMP:20260522T162441Z
LOCATION:Poster Island B
SUMMARY:Cost-Benefit Analysis of a 22nm ASIC ML-KEM Accelerator for RISC-V 
 Secure Elements - Ivan Sarno\, Stefano Di Matteo\, Emanuele Valea\, Hack
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/PB9JGQ/
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BEGIN:VEVENT
UID:pretalx-eu-summit-2026-NWCNCN@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T134000
DTEND;TZID=CET:20260610T135000
DESCRIPTION:The emergence of the open-source RISC-V Instruction Set Archite
 cture has significantly democratized CPU and SoC design across a wide rang
 e of applications. By enabling companies to implement and customize their 
 own processor architectures\, rather than relying on proprietary solutions
  from a few vendors\, RISC-V allows architectures to be tailored to specif
 ic application requirements. However\, CPU and SoC development remains com
 plex and demands substantial design and verification expertise. To address
  this challenge\, several academic and industrial reference platforms have
  been introduced to accelerate RISC-V–based SoC development. This abstra
 ct presents ALPES\, a versatile SoC platform built around cores from the O
 penHW Foundation. ALPES includes an application-class chipset based on the
  CVA6 processor\, as well as multiple secondary chipsets built around the 
 CV32E40P core\, targeting safe and secure real-time use cases. ALPES provi
 des a robust\, pre-verified foundation for ASIC projects\, supporting seve
 ral research projects focused on the RISC-V ecosystem.
DTSTAMP:20260522T162441Z
LOCATION:Poster Island D
SUMMARY:ALPES: Advanced Low-Power Edge Skeleton - Emanuele Valea\, JEREMIE 
 PESCATORE
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/NWCNCN/
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