Christoph Hazott
Christoph Hazott received his M.Sc. degree in Embedded Systems Design from the University of Applied Sciences Hagenberg, Austria, in 2012. After completing his master’s studies, he joined Infineon Technologies AG, where he worked in the Test Engineering Department. In 2021, he became a PhD student at the Institute for Complex Systems, Johannes Kepler University Linz, Austria, and received his PhD in Computer Science in 2025. He has published several papers in international conferences and journals, including ASP-DAC, ETS, DDECS, FDL, and Integration, the VLSI Journal. Since October 2025, he has been with MINRES Technologies. His current research interests include RISC-V, SystemC/TLM-based virtual prototyping, and the testing and analysis of embedded HW/SW systems.
Session
Hardware Description Languages (HDLs) have evolved from traditional Register Transfer Level (RTL) modeling over High-level Synthesis (HLS) towards todays generative approaches. Although modern HDLs often assert technical advantages, directly comparable evaluations across HDL paradigms remain scarce.
This work introduces a year-long, community-driven tournament, designed to enable reproducible comparison of HDLs under uniform conditions. A RISC-V microarchitecture is independently implemented in multiple HDLs and evaluated within a standardized, GitHub-based framework. Since the framework provides identical conditions, differences can be related to how an HDL enables hardware realization. To ensure the quality of this tournament, all results are public, reproducible, and objectively evaluated, providing transparent evidence of HDL-specific strengths and trade-offs. Through contribution, participants can systematically demonstrate the capabilities of their preferred HDL. The collected implementations can further be used as common reference basis for research, education, and reproducible comparison of HDL approaches.