BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//pretalx//cfp.riscv-europe.org//eu-summit-2026//speaker//UCKCM8
BEGIN:VTIMEZONE
TZID:CET
BEGIN:STANDARD
DTSTART:20001029T040000
RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=10
TZNAME:CET
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
END:STANDARD
BEGIN:DAYLIGHT
DTSTART:20000326T030000
RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=3
TZNAME:CEST
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
END:DAYLIGHT
END:VTIMEZONE
BEGIN:VEVENT
UID:pretalx-eu-summit-2026-QZVQMY@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T132000
DTEND;TZID=CET:20260610T133000
DESCRIPTION:Hardware Description Languages (HDLs) have evolved from traditi
 onal Register Transfer Level (RTL) modeling over High-level Synthesis (HLS
 ) towards todays generative approaches. Although modern HDLs often assert 
 technical advantages\, directly comparable evaluations across HDL paradigm
 s remain scarce.\nThis work introduces a year-long\, community-driven tour
 nament\, designed to enable reproducible comparison of HDLs under uniform 
 conditions. A RISC-V microarchitecture is independently implemented in mul
 tiple HDLs and evaluated within a standardized\, GitHub-based framework. S
 ince the framework provides identical conditions\, differences can be rela
 ted to how an HDL enables hardware realization. To ensure the quality of t
 his tournament\, all results are public\, reproducible\, and objectively e
 valuated\, providing transparent evidence of HDL-specific strengths and tr
 ade-offs. Through contribution\, participants can systematically demonstra
 te the capabilities of their preferred HDL. The collected implementations 
 can further be used as common reference basis for research\, education\, a
 nd reproducible comparison of HDL approaches.
DTSTAMP:20260522T162358Z
LOCATION:Poster Island A
SUMMARY:RISC-V Tournament: Battle of HDLs - Christoph Hazott
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/QZVQMY/
END:VEVENT
END:VCALENDAR