Eloi Merino
Received his B.Sc. in Informatics Engineering in 2025 from Universitat Politècnica de Catalunya (UPC) and is pursuing a M.Sc. in Research and Innovation in Informatics, with a focus on HPC systems, from the same university. He joined the Design Verification team at the Barcelona Supercomputing Center (BSC) in 2024. His research interests include high performance computer architecture, functional verification, and memory subsystem verification.
Session
This paper presents the riscv-test-platform, an enhanced set of environments built upon the riscv-test-env, designed to facilitate the execution of tests and benchmarks on RISC-V architectures atop bare-metal environments. Their balance between code complexity and features make them a flexible platform to execute software in both simulated and FPGA environments, bridging the gap between the two platforms, with the advantages that each provide. The result is a set of four environments that mimic the functionalities of the original riscv-test-env, with the addition of some benchmarking features, which exercise more parts of RTL designs and help verification teams spot mismatches in the early stages of development.