This paper presents Sail-RISCV-WASM, which addresses three common limitations of existing browser-based RISC-V tools: fragmented capabilities, limited configurability, and disconnected build/debug pipelines. The system uses sail-riscv as its semantic baseline and compiles it to WebAssembly, forming a three-layer architecture in a pure browser environment: a Sail decode/execute layer, a toolchain layer (gas/ld/objdump), and a metadata layer based on the RISC-V UDB. Based on this architecture, the paper defines two core workflows. The first is configuration-sensitive online encode/decode with instruction metadata navigation for cross-configuration behavior comparison. The second is an in-browser assemble-to-ELF, execute, and interactive debugging loop, supporting instruction-level stepping, source-line stepping, synchronized source/disassembly views, and register/memory tracing. Results show that the system provides a complete single-page flow from exploration to build to diagnosis, with strong extension coverage and configuration flexibility.

The Sail RISC-V Model can generate an executable file from its formal specification,. Currrently RISC-V tests only provides limited test cases and cannot comprehensively test your RISC-V implementation. Some chips may use self-developed simulators for testing, but they cannot obtain formal verification-based guarantees like RISC-V Sail Model, nor can they offer full configurability. This work introduces a new test framework that uses the RISC-V Sail Model as the ref model, ensuring the model's completeness and accuracy. To improve simulation performance, we choose to use Pydrofoil, which is an improved version of the Sail Model that delivers ultra-high performance. To enhance test compatibility and usability, we provide a set of simple test interfaces (including register access, memory access, etc.) and support customizing model configurations. Currently, it has successfully integrated tests for some open-source RISC-V implementations.