BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//pretalx//cfp.riscv-europe.org//eu-summit-2026//speaker//UVSUHJ
BEGIN:VTIMEZONE
TZID:CET
BEGIN:STANDARD
DTSTART:20001029T040000
RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=10
TZNAME:CET
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
END:STANDARD
BEGIN:DAYLIGHT
DTSTART:20000326T030000
RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=3
TZNAME:CEST
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
END:DAYLIGHT
END:VTIMEZONE
BEGIN:VEVENT
UID:pretalx-eu-summit-2026-NTCH3P@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T134000
DTEND;TZID=CET:20260610T135000
DESCRIPTION:We present a coverage-driven framework that optimizes RISC-V sm
 oke regressions by decomposing VCS coverage into feature-specific subsets 
 via tag-based pattern matching\, ranking tests via greedy set cover\, and 
 flagging runtime outliers. Applied to a 978-test production suite drawn fr
 om a larger regression pool of 10\,000 tests\, the framework cut smoke tes
 ts by 40% and peak test runtime by 63%\, while improving coverage on key a
 rchitectural features-including +64% (SMRNMI)\, +53% (timer)\, and +25% (c
 ounters)-with modest regressions on a few features (median <3%)\, all with
 in project thresholds.
DTSTAMP:20260522T162519Z
LOCATION:Poster Island A
SUMMARY:Coverage-Directed Smoke Regression Optimization via Greedy Set Cove
 r for RISC-V Verification - Anish Jaltare\, Abhishek Rajgadia\, Shubham Si
 ngla\, Radha Govindaradjou
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/NTCH3P/
END:VEVENT
BEGIN:VEVENT
UID:pretalx-eu-summit-2026-BREVML@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T154000
DTEND;TZID=CET:20260610T155000
DESCRIPTION:Writing verification stimulus for RISC-V processors requires de
 ep expertise across ISA specifications\, microarchitectural implementation
 \, and test framework APIs. We present an LLM-driven multi-agent framework
  that transforms a brief natural-language scenario description into a comp
 rehensive\, executable RISC-V test generator. Five specialized AI agents f
 orm a sequential enrichment\npipeline: an ISA expert expands intent into a
 rchitecturally complete scenarios\, an RTL analyst reads hardware source c
 ode to inject microarchitecture-targeted stress patterns\, a framework spe
 cialist maps steps to concrete API calls\, a builder synthesizes deployabl
 e code\, and a validator ensures correctness through static checks and ins
 truction-set-simulator execution. On the RISC-V Svadu extension\, a 3-line
  scenario yields 490 lines of validated\, simulation-passing code in under
  13 minutes—a ∼40× speedup versus an estimated∼8 hours of manual ef
 fort.
DTSTAMP:20260522T162519Z
LOCATION:Poster Island A
SUMMARY:LLM-Driven Multi-Agent Framework for Automated RISC-V Verification 
 Stimulus Generation - Kavya Sri Endukuri\, Nicholas Matus\, Radha Govindar
 adjou
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/BREVML/
END:VEVENT
BEGIN:VEVENT
UID:pretalx-eu-summit-2026-CBLJYX@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T161000
DTEND;TZID=CET:20260610T162000
DESCRIPTION:Verifying modern RISC-V cores requires qualifying every merge r
 equest (MR) against a large and evolving test space spanning ISA extension
 s\, micro-architectural features\, and system-level scenarios. Manually se
 lecting appropriate tests for each MR is time-consuming and error-prone\, 
 and does not scale with the rate of RTL changes. This work presents an AI-
 driven testlist generator that automatically derives MR-specific regressio
 n lists for a production RISC-V core verification environment. The tool an
 alyzes Git diffs for an MR\, infers impacted features using a combination 
 of static rules and large language models (LLMs)\, and synthesizes targete
 d regressions across multiple test generators. The resulting flow reduces 
 MR-qualification effort\, improves repeatability\, and provides a concrete
  path toward coverage-driven\, closed-loop test selection for RISC-V core 
 verification.
DTSTAMP:20260522T162519Z
LOCATION:Poster Island A
SUMMARY:AI-Driven Testlist Generation for RISC-V Core Verification - Vikas 
 Dubey\, Abhishek Rajgadia\, Shubham Singla\, Radha Govindaradjou
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/CBLJYX/
END:VEVENT
END:VCALENDAR