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UID:pretalx-eu-summit-2026-8VDLDD@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T133000
DTEND;TZID=CET:20260610T134000
DESCRIPTION:Functional verification dominates modern SoC development effort
 \, yet migrating simulation testbenches to FPGA emulation typically requir
 es proprietary tools\, expensive licenses\, and\n  significant manual RTL 
 adaptation-particularly for designs using DPI-C calls\, multi-cycle timing
  blocks\, or system tasks like $display and $finish. We present Loom\, a f
 ully open-source\n   toolchain that automatically transforms unmodified si
 mulation-grade SystemVerilog into FPGA-synthesizable RTL with complete hos
 t communication infrastructure. Built on Yosys\, Loom\n  applies five comp
 osable compiler passes-memory shadowing\, reset extraction\, DPI-C bridge 
 instrumentation\, scan chain insertion\, and AXI-Lite emulation wrapping-t
 o close the semantic\n  gap between simulation and emulation. We validate 
 Loom end-to-end on a Snitch RISC-V core running on a Xilinx Alveo U250 wit
 h no manual source modifications\, demonstrating DPI argument\n   passing\
 , scan-based state capture/restore\, and host memory preloading via PCIe X
 DMA.
DTSTAMP:20260522T162446Z
LOCATION:Poster Island A
SUMMARY:Loom: An Open-Source Toolchain for Automatic FPGA Emulation of Simu
 lation-Grade SystemVerilog - Florian Zaruba
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/8VDLDD/
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