Radiation-induced bit-flips in on-chip memories threaten the reliability of processor-based systems, particularly in aerospace applications. This work introduces ECC-based hardening for the HPDcache, an open-source L1 data cache compatible with RISC-V cores (e.g., CVA6). The design enables Single Error Correction and Double Error Detection (SECDED), thereby protecting SRAMs from transient faults. A scrubber further mitigates multi-bit errors by periodically refreshing cachelines. Implementation of an 8 KiB cache configuration in 45 nm technology shows a 2.1% core area overhead and an 8% clock frequency reduction. This is a first step towards a fully open-source RISC-V core with both safety features and a high-performance memory subsystem to address the increasing computing demand in aerospace applications.