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UID:pretalx-eu-summit-2026-G8FEKT@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T134000
DTEND;TZID=CET:20260610T135000
DESCRIPTION:Radiation-induced bit-flips in on-chip memories threaten the re
 liability of processor-based systems\, particularly in aerospace applicati
 ons. This work introduces ECC-based hardening for the HPDcache\, an open-s
 ource L1 data cache compatible with RISC-V cores (e.g.\, CVA6). The design
  enables Single Error Correction and Double Error Detection (SECDED)\, the
 reby protecting SRAMs from transient faults. A scrubber further mitigates 
 multi-bit errors by periodically refreshing cachelines. Implementation of 
 an 8 KiB cache configuration in 45 nm technology shows a 2.1% core area ov
 erhead and an 8% clock frequency reduction. This is a first step towards a
  fully open-source RISC-V core with both safety features and a high-perfor
 mance memory subsystem to address the increasing computing demand in aeros
 pace applications.
DTSTAMP:20260522T162444Z
LOCATION:Poster Island C
SUMMARY:Flying V: A Radiation-Hardened L1 Data Cache for RISC-V Aerospace P
 rocessors - César Fuguet
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/G8FEKT/
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