Xavier Carril Gil
PhD research engineer in Computer Architecture at Universitat Politècnica de Catalunya (UPC) and the Barcelona Supercomputing Center (BSC), focused on domain-specific hardware acceleration for Post-Quantum Cryptography (PQC) on RISC-V systems. Over 6 years of hands-on experience in hardware design (Jan 2020 – Present), with core expertise in RTL development and contributions spanning verification, physical design, and silicon bring-up. Participated in four silicon test-chip tapeouts (TSMC 65 nm, GlobalFoundries 22 nm, Intel 3). Experienced in custom RISC-V ISA extensions, hardware/software co-design, and FPGA-based High-Level Synthesis (HLS) prototyping as part of a full-stack research workflow for efficient and scalable computing systems.
Session
Recent advances in quantum computing threaten conventional public-key cryptographic algorithms, necessitating the adoption of post-quantum schemes such as ML-KEM and ML-DSA. The performance of these schemes is constrained primarily by two computationally intensive kernels: the Number-Theoretic Transform (NTT) and the Keccak-f1600 permutation.
This work introduces PQCUARK, a scalar RISC-V Instruction Set Architecture (ISA) extension that accelerates both kernels through two tightly integrated units: a packed-SIMD butterfly unit for the NTT and a Keccak engine capable of delivering two rounds per cycle with direct access to the Load-Store Unit.
Implementation of PQCUARK on an RV64 core and deployment on an FPGA achieves up to a 10.1× speedup over NIST reference software and a 4.2× improvement over optimized implementations, surpassing state-of-the-art solutions by factors ranging from 1.4× to 12.3×. ASIC synthesis in GF22-FDSOI demonstrates only an 8% core-area overhead at 1.2 GHz, with no impact on the critical path.