Functional verification of RISC-V multi-core IPs is bottleneck by the sequential nature of convectional CPU-based event driven simulation, where coverage closure timelines scale linearly with core count and configuration complexity. This paper presents a GPU- accelerated parallel simulation framework that offloads stimulus generation, constraint solving, and concurrent coverage computation to GPU hardware while retaining UVM testbench orchestration on the CPU host. The framework employs a heterogeneous partitioning tasks including constrained-random transaction generation, functional coverage bin evaluation, and reference model computation are parallelized across GPU threads using CUDA kernels. The control, DUT RTL simulation, and sequential verification logic, ensuring complete compatibility with existing verification flows. Evaluated on RISC-V IP configurations ranging from 2 to 32 cores with AXI4 interconnect and MESI coherency protocol, the framework achieves up to 22x simulation speedup, reduces coverage closure time from 44 hours to 14 hours, and reaches 99 percent functional coverage versus 93 percent for CPU-only baselines within the same wall clock budget. The GPU acceleration advantage scales near -linearly with core count, making it particularly valuable for emerging many core RISC-V designs targeting automotive and data-center applications. The approach requires no modification to existing RTL or UVM testbench architectures, integrating via a lightweight GPU dispatch layer that operates on standard simulation interfaces.