Verifying modern RISC-V cores requires qualifying every merge request (MR) against a large and evolving test space spanning ISA extensions, micro-architectural features, and system-level scenarios. Manually selecting appropriate tests for each MR is time-consuming and error-prone, and does not scale with the rate of RTL changes. This work presents an AI-driven testlist generator that automatically derives MR-specific regression lists for a production RISC-V core verification environment. The tool analyzes Git diffs for an MR, infers impacted features using a combination of static rules and large language models (LLMs), and synthesizes targeted regressions across multiple test generators. The resulting flow reduces MR-qualification effort, improves repeatability, and provides a concrete path toward coverage-driven, closed-loop test selection for RISC-V core verification.