BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//pretalx//cfp.riscv-europe.org//eu-summit-2026//speaker//WLW7EY
BEGIN:VTIMEZONE
TZID:CET
BEGIN:STANDARD
DTSTART:20001029T040000
RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=10
TZNAME:CET
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
END:STANDARD
BEGIN:DAYLIGHT
DTSTART:20000326T030000
RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=3
TZNAME:CEST
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
END:DAYLIGHT
END:VTIMEZONE
BEGIN:VEVENT
UID:pretalx-eu-summit-2026-BSGU8Y@cfp.riscv-europe.org
DTSTART;TZID=CET:20260611T104000
DTEND;TZID=CET:20260611T105000
DESCRIPTION:This work presents the design of a tightly coupled near-memory 
 computing unit compatible with a preliminary RISC-V Attached Matrix Extens
 ion. The proposed unit is designed to be integrated with a processor core 
 through the Core-V eXtension Interface (CV-X-IF)\, enabling matrix operati
 ons to be decoded and executed directly in a processing unit attached to a
  system's main memory. Instead of moving data into registers prior to comp
 utation\, load instructions specify operand locations in main memory. Memo
 ry access and near-memory computation are deferred until the execution uni
 t requires the operands. To evaluate the feasibility of the proposed archi
 tecture\, a model of the unit is designed\, implemented\, and validated in
  the gem5 architectural simulator. This model serves as a first step to pr
 ove the concept and enables design-space exploration of the architecture. 
 As a preliminary evaluation\, a quantized convolutional neural network wor
 kload is executed on the simulator to assess the potential performance ben
 efits of the approach\, achieving a 47x speed-up with respect to a simulat
 ed processor baseline.
DTSTAMP:20260522T162730Z
LOCATION:Poster Island B
SUMMARY:Tightly Coupled Near-Memory Matrix Unit for RISC-V Embedded Computi
 ng - Juan Granja
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/BSGU8Y/
END:VEVENT
END:VCALENDAR