The development of our tightly coupled SIMD/Vector accelerator for matrix operations requires extending the RISC-V instruction set. Special compiler support is required for this extension. Our methodology starts from a Sail description of the ISA extension and generates the compiler target description data. The instructions are described in Sail and are tested in the generated simulator. The compiler is generated from the description model and is tested with the accelerator implemented in hardware. The experimental results suggest that for matrix multiplication we obtained speed-ups up to 1413x compared to an ARM A72 core.