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UID:pretalx-eu-summit-2026-ZFMXUE@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T141000
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DESCRIPTION:Deploying high-performance AI inference on autonomous drones re
 quires a precise balance between computational throughput and a strict 1W 
 power envelope. This paper presents a vertical design space exploration (D
 SE) of the RISC-V Gemmini accelerator\, scaling from 8x8 to 32x32 mesh con
 figurations in the SkyWater 130nm process. Through an end-to-end evaluatio
 n using a YOLOv4-tiny model on the VisDrone dataset\, we demonstrate a 74.
 75% reduction in model memory footprint via INT8 quantization and a speedu
 p of up to 2352x compared to a RISC-V CPU baseline. Our results indicate t
 hat while the 32x32 mesh excels in peak throughput\, the 16x16 mesh repres
 ents the optimal “sweet spot” for 1W-limited drone chiplets\, combinin
 g high performance with manageable leakage and area.
DTSTAMP:20260522T162355Z
LOCATION:Poster Island D
SUMMARY:1W Envelope: Area-Energy Trade-offs of Scalable RISC-V Systolic Arr
 ays in Sky130 - Daniel Klünder
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/ZFMXUE/
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