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UID:pretalx-eu-summit-2026-ETWPMQ@cfp.riscv-europe.org
DTSTART;TZID=CET:20260611T120000
DTEND;TZID=CET:20260611T121500
DESCRIPTION:RISC-V's Zvvm matrix extension stores all tile state in the sta
 ndard V register file and derives tile geometry algebraically from VLEN\, 
 SEW\, and a new aspect-ratio field λ. This yields arithmetic intensity th
 at scales with VLEN: a binary compiled at VLEN=256 delivers higher through
 put at VLEN=65536 with no recompilation. The same partial-VL mechanism tha
 t enables one-column-at-a-time embedded streaming also drives full HPC bul
 k tiling\, while microscaling is integrated via vm-bit opcode aliasing wit
 h no new architectural state.\n\nTile dimensions are not programmer-specif
 ied constants — they are consequences of existing parameters. The tile i
 s always square: M = N = VLEN/(SEW×λ)\, with inner dimension K\\_eff = 
 λ×W×LMUL. Arithmetic intensity (M/2) grows proportionally with VLEN\, a
 nd the ratio of intensity to cache-to-VRF bandwidth remains constant — a
  provable algebraic identity with no equivalent in Arm SME or Intel AMX.\n
 \nZvvm's geometry knobs form an intent vocabulary expressed from both side
 s: software selects LMUL and VL to control K\\_eff depth and streaming gra
 nularity\; hardware determines λ and VLEN to shape the tile for its datap
 ath. Setting VL = K\\_eff with LMUL = 1 gives portable streaming\; increas
 ing LMUL or computing multiple C panels trades register pressure for compu
 te intensity — all via the same opcode.\n\nMicroscaling (MX) support is 
 integrated by aliasing the vm bit in FP multiply-accumulate opcodes\, intr
 oducing no new encoding space\, registers\, or modes.
DTSTAMP:20260522T162431Z
LOCATION:Plenary
SUMMARY:All The Scaling\, No New State: One Matrix ISA with Microarchitectu
 ral Freedom - Dr. Philipp Tomsich
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/ETWPMQ/
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