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UID:pretalx-eu-summit-2026-EDH9EE@cfp.riscv-europe.org
DTSTART;TZID=CET:20260609T142000
DTEND;TZID=CET:20260609T143000
DESCRIPTION:We present HBENCH\, a microbenchmark suite for instruction-leve
 l characterization of RISC-V (scalar and RISC-V Vector Extension (RVV)) an
 d x86 (scalar and Advanced Vector Extensions (AVX)2)\, enabling accurate s
 imulator performance models. HBENCH maps scalar and vector microkernels to
  gem5 latency groups and reports latency and peak throughput for Floating-
 Point (FP)32\, FP64\, and Integer (INT) operations. We evaluate a Banana P
 i F3 (SpacemiT K1\, X60\, RVV 1.0\, 256-bit Vector Length (VLEN)) and deri
 ve a gem5-compatible performance model. Coverage is validated against RIVE
 C workloads using dominant RVV instruction mixes.\nOur results span over 3
 29 microkernels\, providing per-latency-group latency and throughput\, cac
 he hierarchy probes\, and Instructions Per Cycle (IPC)-based classificatio
 n\, demonstrating HBENCH’s ability to support high-accuracy instruction-
 level performance modeling.
DTSTAMP:20260715T065841Z
LOCATION:Poster Island D
SUMMARY:HBENCH: RISC-V Microbenchmark Suite - Victor Asanza\, Carlos Rojas 
 Morales\, Erick Brandon Cureño Contreras
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/EDH9EE/
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