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UID:pretalx-eu-summit-2026-ZBWRKF@cfp.riscv-europe.org
DTSTART;TZID=CET:20260609T141000
DTEND;TZID=CET:20260609T142000
DESCRIPTION:CHERI extends conventional ISAs with hardware-enforced capabili
 ties to provide fine-grained memory protection and its integration in RISC
 -V is gaining momentum with RVY. As adoption grows\, implementations must 
 be evaluated to ensure working CHERI protection mechanisms. We show that e
 xisting memory-corruption exploit implementations do not directly carry ov
 er to CHERI-enabled architectures\, and that observed exploit failures (i.
 e.\, unsuccessful exploits) do not necessarily imply effective protection.
  To resolve this ambiguity\, we propose a methodology that temporarily dis
 ables CHERI enforcement within a RISC-V VP. Comparing exploit behavior wit
 h and without CHERI enforcement under otherwise identical conditions makes
  it possible to distinguish exploit failure from effective CHERI protectio
 n.
DTSTAMP:20260522T162821Z
LOCATION:Poster Island A
SUMMARY:Distinguishing Exploit Failure from Effective CHERI Protection on R
 ISC-V - Daniel Große\, Manfred Schlägl\, Andreas Hinterdorfer
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/ZBWRKF/
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UID:pretalx-eu-summit-2026-WWSLLF@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T104000
DTEND;TZID=CET:20260610T105000
DESCRIPTION:In recent years\, the executable specification generated from S
 ail-RISC-V has increasingly been considered as a successor to the widely u
 sed Spike ISA Simulator as golden reference for RISC-V\, including the com
 plex and highly configurable RISC-V Vector Extension (RVV). In this paper\
 , we compare the RVV behavior of Sail-RISC-V against Spike using the autom
 ated testing framework RVVTS. While Sail-RISC-V largely matches Spike unde
 r positive testing (0.23% deviations)\, negative testing reveals substanti
 ally more deviations (3.73%)\, highlighting remaining issues in Sail-RISC-
 V’s RVV instruction validity checking under dynamic configurations.
DTSTAMP:20260522T162821Z
LOCATION:Poster Island A
SUMMARY:Sail-RISC-V and Spike for RISC-V Vector: Toward Consistent Golden R
 eference Behavior - Daniel Große\, Manfred Schlägl\, Katharina Ruep
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/WWSLLF/
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