Historically, many architectures have attempted to run ILP32 software on 64-bit ISAs, such as x86-X32, mips-N32, and arm64-ILP32. However, only arm64ilp32 achieved commercial success on Apple Watch OS in a closed-source manner.

Today, we present the commercial deployment of RV64-ILP32 based on Allwinner v861 AI Glasses chips (Dual-Core RISC-V XuanTie C907) 1. This demo showcases AI Glasses running the ILP32 Linux kernel on RVA22S64. Compared to traditional RV32, performance improves significantly: iperf throughput reaches 1.5×, and lmbench shows 1.1–1.2× gains across most tests. Furthermore, another demo runs LP64 applications on an RV64-ILP32 Linux kernel within a 2GB address space for the first time, highlighting this ABI's compatibility, flexibility, and potential. This demo achievement marks a milestone in bringing 64-bit RISC-V architectural benefits to resource-constrained embedded AI devices while maintaining ILP32 memory efficiency based on an open-source software stack.

This demo illustrates ILP32 on RVA (22/23) S64.
Next, call for sponsors for ILP32 on RVA (22/23) U64!

Advanced Interrupt Architecture (AIA) Incoming MSI Controller (IMSIC) is a message-signaled interrupt (MSI) solution designed for the RISC-V External interrupt. However, due to the lack of native support for Software-Interrupt, IPI was forced to mix with IMSIC interrupts. In large systems, inter-processor interrupts (IPIs) occur very frequently and in large numbers, far exceeding the number of device interrupts. To alleviate IPI pressure on the Network-on-Chip (NoC), an interrupt-forwarding router is typically designed. However, the requirement for 2048 interrupt sources in the AIA IMSIC consumes a significant amount of SRAM in the BITMAP design, increasing chip area and cost. To improve IPI doorbell efficiency, hardware logic for merge-and-absorption based on BITMAP also needs to be designed per-hart at the transmitter, but AIA IMSIC's large interrupt sources design makes this design expensive. Furthermore, IMSIC's IPI allows any MSI-capable device to forge an IPI by sending a specific interrupt number, causing unnecessary disruption. To bridge this gap, propose a Software MSI Controller (SMSIC) for AIA, an optional RISC-V hardware component tightly coupled to each hart. The idea of architecturally separating IPIs from external interrupts not only reduces the cost of improving IPI performance in large systems but also aligns with the original intent of the Software Interrupt design in the RISC-V Privileged Specification.