Historically, several architectures have explored running ILP32 software on 64-bit ISAs - including ×86-X32, MIPS-N32, and Arm64-ILP32 - yet only Arm64-ILP32 reached commercial adoption, exclusively within Watch OS as a closed-source implementation.
We now present a new landmark: the first open-source commercial deployment of
RV64ILP32, realized on the Allwinner V881 Al Glasses SoC (Dual-Core XuanTie
(907).
1. Product-Level Demo (V881-based): An Al Glasses device running with
RV64ILP32 Linux kernel. Benchmarks against traditional RV32 Linux kernel demonstrate substantial gains - iperf loopback test throughput improves by 1.5×, while eBPF performance achieves up to 5.7× speedups across test cases
2. Community-Level Demo (QEMU-based): For the first time, LP64 applications execute on an RV64ILP32 Linux kernel, which provides ‡2 GB of separate address spaces, revealing new possibilities for mixed-ABI workloads on RISC-V (20% memory footprint saved v.s. traditional RV64 Linux kernel).

Together, these demonstrations mark a significant milestone: delivering 64-bit RISC-V performance advantages to resource-constrained embedded AI devices, while preserving ILP32 memory/cache efficiency - entirely on an open-source software stack.

The surging demand for VM-based secure containers in the AI Agent era is driving rapid growth in the scale of vCPU deployments. However, the current RISC-V AIA specification co-locates inter-processor interrupts (IPIs) and device interrupts within the IMSIC, causing hardware resource overhead to scale multiplicatively with both the per-file size and the total count of S/VS-files — a structural coupling that fundamentally limits vCPU interrupt pass-through scalability.
To address this, we propose the Software-interrupt MSI Controller (SMSIC), an AIA extension that explicitly decouples IPI from the IMSIC external interrupt hierarchy and establishes a dedicated MSI delivery path for the software interrupts defined in the RISC-V privileged specification. By fully decoupling the IPI path from the device interrupt path, SMSIC reduces the per-VS-file IPI resource to a single interrupt entry, comprising only one enable bit and one pending bit, thereby supporting large-scale VS-file deployment at minimal hardware cost (for both the per-hart and SoC IPI merging & absorption components). Furthermore, with the IPI path isolated, IOMMU MRIF can scale the number of virtualization interrupt files to support larger-scale deployments of vCPU interrupt pass-through, effectively taking over the scalability role from native IMSIC VS-files.

The increasing computational demands of modern AI workloads necessitate a holistic architectural approach to AI acceleration on RISC-V processors. This talk presents the XuanTie Tensor Processing Engine (TPE), a RISC-V-based Attached Matrix Extension (AME) engine designed to address AI acceleration across three dimensions: ISA, microarchitecture, and software ecosystem.
At the ISA level, the TPE adopts the in-progress RISC-V AME specification, featuring dedicated tensor registers and a comprehensive instruction set encompassing matrix multiply-accumulate, element-wise, special function, reduction, and load/store operations with broad data type support including INT4, FP8, FP16, and micro-scaling formats.
At the microarchitecture level, the design incorporates a matrix engine achieving 2 TOPS/GHz at INT8/FP8, a concurrent vector engine with hardware-accelerated non-linear functions, and a layered memory subsystem featuring a coherent tensor cache and data prefetch engine.
A full-stack software ecosystem spanning LLVM toolchain to graph execution runtime completes the solution.
Experimental results on the XuanTie C930 cluster demonstrate 99% FP16 GEMM utilization. We discuss key design trade-offs and implications for the evolving RISC-V AME standard.