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UID:pretalx-eu-summit-2026-GQUDKS@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T130000
DTEND;TZID=CET:20260610T133000
DESCRIPTION:Historically\, many architectures have attempted to run ILP32 s
 oftware on 64-bit ISAs\, such as x86-X32\, mips-N32\, and arm64-ILP32. How
 ever\, only arm64ilp32 achieved commercial success on Apple Watch OS in a 
 closed-source manner.\n\nToday\, we present the commercial deployment of R
 V64-ILP32 based on Allwinner v861 AI Glasses chips (Dual-Core RISC-V XuanT
 ie C907) [1]. This demo showcases AI Glasses running the ILP32 Linux kerne
 l on RVA22S64. Compared to traditional RV32\, performance improves signifi
 cantly: iperf throughput reaches 1.5×\, and lmbench shows 1.1–1.2× gai
 ns across most tests. Furthermore\, another demo runs LP64 applications on
  an RV64-ILP32 Linux kernel within a 2GB address space for the first time\
 , highlighting this ABI's compatibility\, flexibility\, and potential. Thi
 s demo achievement marks a milestone in bringing 64-bit RISC-V architectur
 al benefits to resource-constrained embedded AI devices while maintaining 
 ILP32 memory efficiency based on an open-source software stack.\n\n[1]: ht
 tps://www.cnx-software.com/2026/01/04/allwinner-v861-dual-core-64-bit-risc
 -v-ai-camera-sip-features-128mb-ddr3l-4k-h-265-h-264-video-encoder/\n\nThi
 s demo illustrates ILP32 on RVA (22/23) S64.\nNext\, call for sponsors for
  ILP32 on RVA (22/23) U64!
DTSTAMP:20260522T162353Z
LOCATION:Devzone
SUMMARY:Running ILP32 on RVA(22/23)S64: AI Glasses Product Demo - GUO Ren
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/GQUDKS/
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UID:pretalx-eu-summit-2026-LQRAW3@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T132000
DTEND;TZID=CET:20260610T133000
DESCRIPTION:Advanced Interrupt Architecture (AIA) Incoming MSI Controller (
 IMSIC) is a message-signaled interrupt (MSI) solution designed for the RIS
 C-V External interrupt. However\, due to the lack of native support for So
 ftware-Interrupt\, IPI was forced to mix with IMSIC interrupts. In large s
 ystems\, inter-processor interrupts (IPIs) occur very frequently and in la
 rge numbers\, far exceeding the number of device interrupts. To alleviate 
 IPI pressure on the Network-on-Chip (NoC)\, an interrupt-forwarding router
  is typically designed. However\, the requirement for 2048 interrupt sourc
 es in the AIA IMSIC consumes a significant amount of SRAM in the BITMAP de
 sign\, increasing chip area and cost. To improve IPI doorbell efficiency\,
  hardware logic for merge-and-absorption based on BITMAP also needs to be 
 designed per-hart at the transmitter\, but AIA IMSIC's large interrupt sou
 rces design makes this design expensive. Furthermore\, IMSIC's IPI allows 
 any MSI-capable device to forge an IPI by sending a specific interrupt num
 ber\, causing unnecessary disruption. To bridge this gap\, propose a Softw
 are MSI Controller (SMSIC) for AIA\, an optional RISC-V hardware component
  tightly coupled to each hart. The idea of architecturally separating IPIs
  from external interrupts not only reduces the cost of improving IPI perfo
 rmance in large systems but also aligns with the original intent of the So
 ftware Interrupt design in the RISC-V Privileged Specification.
DTSTAMP:20260522T162353Z
LOCATION:Poster Island D
SUMMARY:SMSIC: Software-Interrupt MSI Controller for RISCV AIA in Large-Sca
 le NoC Systems - GUO Ren
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/LQRAW3/
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