The emergence of the open-source RISC-V Instruction Set Architecture has significantly democratized CPU and SoC design across a wide range of applications. By enabling companies to implement and customize their own processor architectures, rather than relying on proprietary solutions from a few vendors, RISC-V allows architectures to be tailored to specific application requirements. However, CPU and SoC development remains complex and demands substantial design and verification expertise. To address this challenge, several academic and industrial reference platforms have been introduced to accelerate RISC-V–based SoC development. This abstract presents ALPES, a versatile SoC platform built around cores from the OpenHW Foundation. ALPES includes an application-class chipset based on the CVA6 processor, as well as multiple secondary chipsets built around the CV32E40P core, targeting safe and secure real-time use cases. ALPES provides a robust, pre-verified foundation for ASIC projects, supporting several research projects focused on the RISC-V ecosystem.