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UID:pretalx-eu-summit-2026-NWCNCN@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T134000
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DESCRIPTION:The emergence of the open-source RISC-V Instruction Set Archite
 cture has significantly democratized CPU and SoC design across a wide rang
 e of applications. By enabling companies to implement and customize their 
 own processor architectures\, rather than relying on proprietary solutions
  from a few vendors\, RISC-V allows architectures to be tailored to specif
 ic application requirements. However\, CPU and SoC development remains com
 plex and demands substantial design and verification expertise. To address
  this challenge\, several academic and industrial reference platforms have
  been introduced to accelerate RISC-V–based SoC development. This abstra
 ct presents ALPES\, a versatile SoC platform built around cores from the O
 penHW Foundation. ALPES includes an application-class chipset based on the
  CVA6 processor\, as well as multiple secondary chipsets built around the 
 CV32E40P core\, targeting safe and secure real-time use cases. ALPES provi
 des a robust\, pre-verified foundation for ASIC projects\, supporting seve
 ral research projects focused on the RISC-V ecosystem.
DTSTAMP:20260522T162454Z
LOCATION:Poster Island D
SUMMARY:ALPES: Advanced Low-Power Edge Skeleton - Emanuele Valea\, JEREMIE 
 PESCATORE
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/NWCNCN/
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