The exponential growth in RISC-V processor complexity challenges traditional functional verification. Both directed testing and constrained-random simulation are inefficient for modern architectural designs. While hardware fuzzing has emerged as a powerful alternative for uncovering deep microarchitectural bugs, existing software-based fuzzers are severely bottlenecked by slow RTL simulation speeds and suboptimal mutation strategies that lack adaptive guidance.We propose AdaMut-RV, a high-throughput, FPGA-accelerated fuzzing framework specifically optimized for RISC-V processor verification. Unlike software-bound solutions, AdaMut-RV offloads both the processor and the fuzzer onto FPGA hardware, enabling MHz-scale execution speeds. The core innovation of AdaMut-RV is an intelligent mutation-operator scheduler based on the Multi-Armed Bandit (MAB) reinforcement learning algorithm. By categorizing AFL-inspired mutation operators into nine distinct classes, our scheduler dynamically prioritizes those that yield the highest coverage gains based on real-time hardware feedback. This dynamic scheduling mechanism accelerates the exploration of processor design spaces and critical corner-case logic. Preliminary results demonstrate that AdaMut-RV significantly outperforms state-of-the-art software-based fuzzers. It achieves higher Control and Status Register Coverage while reaching the same coverage targets at a significantly faster rate.